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| K4C89183AF - 1 - rev. 0.7 jan. 2005 288mb x18 network-dram2 specification version 0.7
K4C89183AF - 2 - rev. 0.7 jan. 2005 revision history version 0.0 (oct. 2002) - first release version 0.01 (nov. 2002) - changed die revision from d-die to f-die - corrected typo - corrected dqs to ds and qs(dqs -> ds and qs) in ac timing table and timing diagram. version 0.1 (apr. 2003) - added 800mbps(400mhz) product - changed operating temperature from ta to tc. - changed capacitance of addr/cmd/clk - changed tdss(ds input falling edge to clock setup time) - added cl7 for 800mbps - deleted tsop package outline version 0.11 (apr. 2003) - corrected typo in page 3.(deleted bi-directional strobe) - corrected min. vref to vddq/2x95% in page 7 version 0.2 (aug. 2003) - added package physical dimension - extracted 800mbps(g7) binning from target spec ( g7 will be added in the future) - changed dc test condition - changed low frequency spec like below - changed ac test load picture version 0.3 (nov. 2003) - changed packge type from die-exposed to full molded - changed package code in partnumber from to min max min max addr/cmd/clk 1.5 2.5 1.5 3.0 from to f6 fb f5 g7 f6 fb f5 cl4 0.9 0.9 1.0 0.75 0.75 0.8 1.0 cl5 0.9 0.9 1.0 0.75 0.75 0.8 1.0 cl6 0.9 0.9 1.0 0.75 0.75 0.8 1.0 cl7 - - - 0.75 - - - from to changed point idd1s,idd2n,idd2p,idd5,idd6 idd1s,i dd2n,idd2p,idd5b,i dd6 changed condition - idd4w, idd4r newly inserted from to unit : ns f6 fb f5 f6 fb f5 tck max@cl=4 7.5 7.5 7.5 6.0 6.0 6.0 tck max@cl=5 7.5 7.5 7.5 6.0 6.0 6.0 tck max@cl=6 7.5 7.5 7.5 6.0 6.0 6.0 K4C89183AF - 3 - rev. 0.7 jan. 2005 version 0.31 (mar., 2004) - corrected typo. in page 7 (changed operati ng temperature to 85?c, case temperature) version 0.4 (jun., 2004) - changed from "target" to "preliminary" - changed min. tck@cl5 to 3.5ns in "-f6" version 0.5 (aug., 2004) - deleted self-refresh function and bl2 from spec version 0.51 (aug., 2004) - corrected error in page 54, "package out line draw ing". (just 4 balls were missing in drawing) version 0.6 (nov., 2004) - deleted "preliminary" - changed current value in page 9 version 0.7 (jan., 2005) - deleted the tdqsqa in page 11 - deleted the tssk in page 11 from to f6 f6 t ck clock cycle time (min) cl = 4 4.0 ns 4.0 ns cl = 5 3.33 ns 3.5 ns cl = 6 3.0ns 3.0ns K4C89183AF - 4 - rev. 0.7 jan. 2005 4,194,304-words x 4 banks x 18-bits double data rate network-dram description K4C89183AF is a cmos double data ra te network-dram containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits. k4c8918 3af feature a fully synchr onous operation referenced to clock edge whereby all opera - tions are synchronized at a clock input wh ich enables high performance and simple us er interface coexiste nce. K4C89183AF can op er- ate fast core cycle compared with regular ddr sdram. K4C89183AF is suitable for server, network and other applicati ons where large memory density and low power consumption are required. the output driver for network-dram is capable of high quality fast data transfer under light loading condition. features parameter K4C89183AF f6 fb f5 t ck clock cycle time (min) cl = 4 4.0 ns 4.5 ns 5.0 ns cl = 5 3.5 ns 3.75 ns 4.5 ns cl = 6 3.0ns 3.33 ns 4.0 ns t rc random read/write cycle time (min) 20.0 ns 22.5 ns 25 ns t rac random access time (min) 20.0 ns 22.5 ns 25 ns i dd1s operating current (single bank) (max) 320ma 300ma 280ma i dd2p power down current (max) 70ma 65ma 60ma ? fully synchronous operation - double data rate (ddr) - data input/output are synchronized with both edges of ds / qs. - differential clock (clk and clk ) inputs - cs , fn and all address input signals are sampled on the positive edge of clk. - output data (dqs and qs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 3.0 ns minimum - clock : 333 mhz maximum - data : 666 mbps/pin maximum ? quad independent banks operation ? fast cycle and short latency ? uni-directional data strobe ? distributed auto-refresh cycle in 3.9us ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length - cas laatency = 4, 5, 6 - burst length = 4 ? organization : 4,194,304 words x 4 banks x 18 bits ? power supply voltage v dd : 2.5v 0.125v ? v ddq : 1.4v 1.9v ? 1.8v cmos i/o comply with sstl - 1.8 (half strength driver) and hstl ? package : 60ball bga, 1.0mm x 1.0mm ball pitch ? notice : network-dram is tr ademark of samsung electronics., co ltd K4C89183AF - 5 - rev. 0.7 jan. 2005 pin names pin name a0 ~ a14 address input ba0, ba1 bank address dq0 ~ dq17 data input/output cs chip select fn function control pd power down control clk, clk clock input ds/qs write/read data strobe vdd power (+2.5v) v ss ground v ddq power (+1.8v) (for i/o buffer) v ssq ground (for i/o buffer) v ref reference voltage nc no connection ball pitch=1.0 x 1.0mm pin assignment (top view) x18 index v ss dq16 dq15 dq14 dq12 dq11 dq10 dq9 v ref clk a12 a11 a8 a5 v ss dq17 v ss q v dd q dq13 v ss q v dd q v ss q ds v ss clk pd a9 a7 a6 a4 dq0 v dd q v ss q dq4 v dd q v ss q v dd q qs v dd fn cs ba1 a0 a2 a3 v dd dq1 dq2 dq3 dq5 dq6 dq7 dq8 a14 a13 nc ba0 a10 a1 v dd 123456 a b c d e f g h j k l m n p r K4C89183AF - 6 - rev. 0.7 jan. 2005 block diagram clk clk pd dll clock buffer command decoder cs fn control generator signal address buffer mode register upper address latch lower address latch column decoder row decoder bank #3 bank #2 bank #1 bank #0 memory cell array data control and latch circuit burst counter read data buffer write data buffer dq buffer a0 ~ a14 ba0, ba1 refresh counter write address latch address comparator ds dq0 ~ dq17 to each block note : the k4c89183ad configuration is 4 bank of 32768 x 128 x 18 of cell array with the dq pins numbered dq0~dq17. qs K4C89183AF - 7 - rev. 0.7 jan. 2005 absolute maximum ratings caution : conditions outside the limits listed under "absolute maximum ratings" may cause per manent damage to the device. the device is not meant to be operated under conditions outside the limits described in the operational section of this specifi - cation. exposure to "absolute maxi mum ratings" conditions for extended periods may affect device reliability. recommended dc,ac operating conditions (notes : 1) (tcase = 0 ~ 85 o c) symbol parameter rating units notes v dd power supply voltage -0.3 ~ 3.3 v v ddq power supply voltage (for i/o buffer) -0.3 ~ v dd + 0.3 v v in input voltage -0.3 ~ v dd + 0.3 v v out dq pin voltage -0.3 ~ v ddq + 0.3 v v ref input reference voltage -0.3 ~ v ddq + 0.3 v t opr operating temperature 0 ~ 85 o c case temp. t stg storage temperature -55 ~ 150 o c t solder soldering temperature(10s) 260 o c p d power dissipation 2 w i out short circuit output current 50 ma symbol parameter min typ max units notes v dd power supply voltage 2.375 2.5 2.625 v v ddq power supply voltage (for i/o buffer) 1.7 1.8 1.9 v v ref input reference voltage v ddq /2x95% v ddq /2 v ddq /2x105% v 2 v ih (dc) input dc high voltage v ref +0.125 - v ddq +0.2 v 5 v il (dc) input dc low voltage -0.1 - v ref -0.125 v 5 v ick (dc) differential clock dc input voltage -0.1 - v ddq +0.1 v 10 v id (dc) input differential voltage. clk and clk inputs (dc) 0.4 - v ddq +0.2 v 7,10 v ih (ac) input ac high voltage v ref +0.2 - v ddq +0.2 v 3,6 v il (ac) input ac low voltage -0.1 - v ref -0.2 v 4,6 v id (ac) input differential voltage. clk and clk inputs (ac) 0.55 - v ddq +0.2 v 7,10 v x (ac) differential ac input cross point voltage v ddq /2-0.125 - v ddq /2+0.125 v 8,10 v iso (ac) differential clock ac middle level v ddq /2-0.125 - v ddq /2+0.125 v 9,10 K4C89183AF - 8 - rev. 0.7 jan. 2005 1. all voltages are referenced to vss, vssq. 2. v ref is expected to track variations in vd dq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% of v ref (dc). 3. overshoot iimit : v ih (max.) = vddq + 0.7v with a pulse width <= 5ns 4. undershoot iimit : v il (min.) = -0.7v with a pulse width <= 5ns 5. v ih (dc) and v il (dc) are levels to maintain the current logic state. 6. v ih (ac) and v il (ac) are levels to change to the new logic state. 7. v id is magnitude of the differen ce between clk input level and clk input level. 8. the value of vx(ac) is expected to equal vddq/2 of the transmitting device. 9. v iso means [v ick (clk) + v ick (clk )]/2 10. refer to the figure below. notes : 11. in the case of external termination, vtt(te rmination voltage) should be gone in the range of v ref (dc) 0.04v. pin capacitance (v dd = 2.5v, v ddq = 1.8v, f = 1 mhz, ta = 25 o c ) note : these parameters are periodically sampled and not 100% tested. symbol parameter min max delts units c in input pin capacitance 1.5 3.0 0.25 pf c inc clock pin (clk, clk ) capacitance 1.5 3.0 0.25 pf c i/o dq, ds, qs capacitance 2.5 3.5 0.5 pf c nc nc pin capacitance - 1.5 - pf clk clk v ss v id (ac) 0 v differential v iso v ss v ick v iso (min) v x v x v x v x v ick v ick v ick v iso (max) v x v id (ac) K4C89183AF - 9 - rev. 0.7 jan. 2005 dc characteristics and operating conditions (vdd = 2.5v 0.125v, vddq = 1.8v 0.1v, tcase = 0~85 c) parameter symbol max units notes f6 fb f5 operating current one bank read or write operation; t ck = min, i rc = min, i out = 0ma; burst length = 4, cas latency = 6, free running qs mode; 0v v in v il(ac) (max.), v ih(ac) (min.) v in v ddq; address inputs change up to 2 times during minimum i rc , read data change twice per clock cycle i dd1s 320 300 280 ma 1, 2 standby current all banks : inactive state; t ck =min, cs = v ih , pd = v ih ; 0v v in v il (ac)(max.), v ih (ac)(min.) v ih v ddq; other input signals change one time during 4*t ck, dq and ds inputs change twice per clock cycle i dd2n 100 95 90 1 standby (power down) current all banks : inactive state; t ck =min, pd = v il (power down); cas latency = 6, free running qs mode; 0v v in v il (ac)(max), v ih (ac)(min) v in v ddq ; other input signals change one time during 4*t ck , dq and ds inputs are floating(v ddq /2) i dd2p 70 65 60 1 write operating current(4 banks) 4 bank intereaved continuous burst write operation; t ck = min, i rc = min; burst length = 4, cas latency = 6, free running qs mode; 0v v in v il (ac) (max.), v ih (ac)(min.) v in v ddq; address inputs change once per clock cycle, dq and ds inputs change twice per clock cycle i dd4w 650 600 550 1 read operating current(4 banks) 4 bank intereaved continuous burst write operation; t ck = min, i rc = min, i out = 0ma; burst length = 4, cas latency = 6, free running qs mode; 0v v in v il (ac) (max.), v ih (ac)(min.) v in v ddq; address inputs change once per clock cycle, read data change twice per clock cycle i dd4r 650 600 550 1,2 burst auto-refresh current refresh command at every i refc interval; t ck = min, i refc = min; cas latency = 6, free running qs mode; 0v v in v il (ac) (max.), v ih (ac) (min.) v in v ddq; address change up to 2 times during minimum i refc , dq and ds inputs change twice per clock cycle i dd5b 250 235 210 1,3 K4C89183AF - 10 - rev. 0.7 jan. 2005 dc characteristics and operating conditions (vdd = 2.5v 0.125v, vddq = 1.8v 0.1v, tcase = 0~85 c) notes : 1. these parameters depend on the cycle rate and these values are measured at a cycle ra te with the minimum values of t ck , t rc and i rc . 2. these parameters depend on the outp ut loading. the specified values are obtained with the output open. 3. i dd5b is specified under burst refresh condition. actual system should use distributed refresh that meet to t refi specification 4. refer to output dr iver characteristic s for the detail. output driver streng th is selected by extended mode reg ister. parameter symbol min max unit notes input leakage current (0v<=v in <=vddq, all other pins not under test = 0v) i li -5 5 ua output leakage current (output disabled, 0v<=v out <=vddq) i lo -5 5 ua v ref current i ref -5 5 ua normal output driver output dc current (v ddq = 1.7 ~ 1.9v) v oh = 1.420v i oh (dc) -5.6 - ma 4 v ol = 0.280v i ol (dc) 5.6 - 4 strong output driver v oh = 1.420v i oh (dc) -9.8 - 4 v ol = 0.280v i ol (dc) 9.8 - 4 weak output driver v oh = 1.420v i oh (dc) -2.8 - 4 v ol = 0.280v i ol (dc) 2.8 - normal output driver output dc current (v ddq = 1.4 ~ 1.6v) v oh = v ddq - 0.4 i oh (dc) -4 - ma 3 v ol = 0.4v i ol (dc) -4 - 3 strong output driver v oh = v ddq - 0.4 i oh (dc) -8 - 3 v ol = 0.4v i ol (dc) -8 - 3 weak output driver not defined i oh (dc) -- not defined i ol (dc) -- K4C89183AF - 11 - rev. 0.7 jan. 2005 ac characteristics and operating conditions (notes : 1, 2) symbol parameter f6 fb f5 units notes min max min max min max t rc random cycle time 20.0 - 22.5 - 25 - ns 3 t ck clock cycle time c l = 4 4.0 6.0 4.5 6.0 5.0 6.0 3 c l = 5 3.33 6.0 3.75 6.0 4.5 6.0 3 c l = 6 3.0 6.0 3.33 6.0 4.0 6.0 3 t rac random access time - 20.0 - 22.5 - 25 3 t ch clock high time 0.45*t ck - 0.45*t ck - 0.45*t ck -3 t cl clock low time 0.45*t ck - 0.45*t ck - 0.45*t ck -3 t ckqs qs access time from clk -0.45 0.45 -0.45 0.45 -0.5 0.5 3, 8 t qsq data output skew from qs - 0.2 - 0.25 - 0.3 4 t ac data access time from clk -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 t oh data output hold time from clk -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 t hp clk half period ( minium of actual t ch , t cl ) min(t ch , t cl ) - min(t ch , t cl ) - min(t ch , t cl ) -3 t qsp qs(read) pulse width t hp - t qhs - t hp - t qhs - t hp - t qhs -4, 8 t qsqv data output valid time from qs t hp - t qhs - t hp - t qhs - t hp - t qhs -4, 8 t qhs dq, qs hold skew factor - 0.055x t ck +0.17 - 0.055x t ck +0.17 - 0.055x t ck +0.17 t dqss ds(write) low to high setup time 0.8*t ck 1.2*t ck 0.8*t ck 1.2*t ck 0.8*t ck 1.2*t ck 3 t dspre ds(write) preamble pulse width 0.4*t ck - 0.4*t ck - 0.4*t ck -4 t dspres ds first input setup time 0 - 0 - 0 - 3 t dspreh ds first low input hold time 0.3*t ck - 0.3*t ck - 0.3*t ck -3 t dsp ds high or low input pulse width 0.45*t ck 0.55*t ck 0.45*t ck 0.55*t ck 0.45*t ck 0.55*t ck 4 t dss ds input falling edge to clock setup time c l = 4 0.75 - 0.8 - 1.0 - 3, 4 c l = 5 0.75 - 0.8 - 1.0 - 3, 4 c l = 6 0.75 - 0.8 - 1.0 - 3, 4 c l = 7 ------ 3, 4 t dspst ds(write) postamble pulse width 0.45*t ck - 0.45*t ck 0.45*t ck -4 t dspsth ds(write) postamble hold time c l = 4 0.75 - 0.8 - 1.0 - 3, 4 c l = 5 0.75 - 0.8 - 1.0 - 3, 4 c l = 6 0.75 - 0.8 - 1.0 3, 4 c l = 7 ------ 3, 4 t ds data input setup time from ds 0.3 - 0.35 - 0.4 - 4 t dh data input hold time from ds 0.3 - 0.35 - 0.4 - 4 t is command / address input setup time 0.6 - 0.6 - 0.7 - 3 t ih command / address input hold time 0.6 - 0.6 - 0.7 - 3 K4C89183AF - 12 - rev. 0.7 jan. 2005 ac characteristics and operating conditions (notes : 1, 2) (continued) symbol parameter f6 fb f5 units notes min max min max min max t lz data-out low impedance time from clk -0.5 - -0.5 - -0.6 - 3, 6, 8 t hz data-out high impedance time from clk - 0.5 - 0.5 - 0.6 3, 7, 8 t qpdh last output to pd high hold time 0 - 0 - 0 - t pdex power down exit time 0.6 - 0.6 - 0.7 - 3 t t input transition time 0.1 1 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry -0.5*t ck 5 -0.5*t ck 5 -0.5*t ck 53 t refi auto-refresh average interval 0.4 3.9 0.4 3.9 0.4 3.9 us 5 t pause pause time after power-up 200 - 200 - 200 - i rc random read/write cycle time (applicable to same bank) c l = 4 5-5-5- cycle c l = 5 6-6-6- c l = 6 7-7-7- c l = 7 ------ i rcd rda/wra to lal command input delay (applicable to same bank) 111111 i ras lal to rda/wra command input delay (applicable to same bank) c l = 4 4-4-4- c l = 5 5-5-5- c l = 6 6-6-6- c l = 7 ------ i rbd random bank access delay (applicable to other bank) 2-2-2- i rwd lal following rda to wra delay (applicable to other bank) bl = 4 3 - 3 - 3 - i wrd lal following wra to rda delay (applicable to other bank) 1-1-1- i rsc mode register set cycle time c l = 4 7-7-7- c l = 5 7-7-7- c l = 6 7-7-7- c l = 7 i pd pd low to inactive state of input buffer - 2 - 2 - 2 i pda pd high to active state of input buffer 1 - 1 - 1 - i pdv power down mode valid from ref com- mand c l = 4 19 - 19 - 19 - c l = 5 23 - 23 - 23 - c l = 6 25 - 25 - 25 - c l = 7 i refc auto-refresh cycle time c l = 4 19 - 19 - 19 - c l = 5 23 - 23 - 23 - c l = 6 25 - 25 - 25 - c l = 7 i lock dll lock-on time (applicable to rda command) 200 - 200 - 200 - K4C89183AF - 13 - rev. 0.7 jan. 2005 ac test conditions symbol parameter value units notes v ih (min) input high voltage (minimum) v ref + 0.2 v v il (max) input low voltage (maximum) v ref - 0.2 v v ref input reference voltage vddq/2 v v tt termination voltage v ref v v swing input signal peak to peak swing 0.7 v v r differential clock input reference level v x(ac) v v id (ac) input differential voltage 1.0 v slew input signal minimum slew rate 2.5 v/ns v otr output timing measurement reference voltage vddq/2 v 9 v ih min (ac) v ref v il max (ac) v swing vddq vss v tt output slew=(v ih min (ac) - v il max (ac) )/ ? t ? t ? t notes : 1. transition times are measured between v ih min (dc) and v il max (dc) . transition (rise and fall) of input signals have a fixed slope. 2. if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.8*t ck , t ck = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.) 3. these parameters are measured from the differential clock (clk and clk ) ac cross point. 4. these parameters are meas ured from signal transition point of ds crossing v ref level. 5. the t refi (max.) applies to equally distributed refresh method. the t refi (min.) applies to both burst refresh method and distributed refresh method. in such case, the average interval of eight consecutive auto-refresh co mmands has to be more than 400ns always . in other words, the number of auto- refresh cycles which can be performed within 3.2us (8x400ns) is to 8 times in the maximum. 6. low impedance state is speified at vddq/2 0.2v from steady state. 7. high impedance state is sp ecified where output buffer is no longer driven. 8. these parameters depend on the cl ock jitter. these parameters are measured at stable clock. 9. output timing is m easured by using normal driver strength at v ddq = 1.7v ~ 1.9v. output timing is measured by using st rong driver strength at v ddq = 1.4v ~ 1.6v ac test load 25 ? measurement point K4C89183AF - 14 - rev. 0.7 jan. 2005 power up sequence 1. as for pd , being maintained by the low state (< 0.2v) is desirable before a power-supply injection. 2. apply v dd before or at the same time as v ddq . 3. apply v ddq before or at the same time as v ref . 4. start clock (clk, clk ) and maintain stable condition for 200us (min.). 5. after stable power and clock, apply desl and take pd = h. 6. issue emrs to enable dll and to define driver strength and data st robe type. (note : 1) 7. issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note : 1) 8. issue two or more auto -refresh commands. (note:1) 9. ready for normal operation after 200 clocks from extended mode register programming. note : 1. sequence 6, 7 and 8 can be issued in random order. 2. l=logic low, h = logic high desl rda mrs desl rda mrs desl wra ref wra ref desl desl emrs mrs op-code op-code v dd v ddq v ref clk clk pd command address dq ds 200 s(min) i pda l rsc l rsc l refc 2.5v(typ) 1.8v(typ) 0.9v(typ) l refc t pdex 200 clock cycle(min) qs emrs hi-z qs (free running mode) (uni-qs mode) mrs auto refresh cycle normal operation low K4C89183AF - 15 - rev. 0.7 jan. 2005 t ck t ck t ch t cl t is t ih t ipw 1st t is t ih 2nd t is t ih 1st t is t ih 2nd t ipw t is t ih ua, ba t is t ih la t ds t dh clk ck cs fn a0-a14 ba0.ba1 ds dqn (input) ~ ~ basic timing diagrams timing of the clk, clk input timing t ch t cl t ck t t t t v ih v ih(ac) v il(ac) v il clk clk clk v ih v il v id(ac) ck v x v x v x ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command and address t dh t ds t ds t dh dqm (input) ~ ~ ~ ~ t dh t ds data refer to the command truth table. K4C89183AF - 16 - rev. 0.7 jan. 2005 q0 lal (after rda) t is t ih t ch t cl t ck t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq low high-z ck ck input (control & addresses) cas latency = 4 lqs/uqs (output) dq (output) read timing (burst length = 4) low desl lds/uds (input) q1 q2 q3 t ac t ac t oh 0123456789101112131415161718 q0 t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq low high-z cas latency = 5 lqs/uqs (output) dq (output) low q1 q2 q3 t ac t ac t oh note : dq0 to dq17 are aligned with lqs. unidirectional ds/qs mode dq18 to dq35 are aligned with uqs. q0 t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq low high-z cas latency = 6 lqs/uqs (output) dq (output) low q1 q2 q3 t ac t ac t oh K4C89183AF - 17 - rev. 0.7 jan. 2005 q0 lal (after rda) t is t ih t ch t cl t ck t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq high-z ck ck input (control & addresses) cas latency = 4 lqs/uqs (output) dq (output) read timing (burst length = 4) desl lds/uds (input) q1 q2 q3 t ac t ac t oh 0123456789101112131415161718 q0 t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq high-z cas latency = 5 lqs/uqs (output) dq (output) q1 q2 q3 t ac t ac t oh note : dq0 to dq17 are aligned with lqs. lqs/uqs is always assert ed in free running qs mode. unidirectional ds/free running qs mode dq18 to dq35 are aligned with uqs. q0 t ckqs t ckqs t qsp t qsp t ckqs t qsq t lz t qsqv t ac t qsqv t qsq t hz t qsq high-z cas latency = 6 lqs/uqs (output) dq (output) q1 q2 q3 t ac t ac t oh K4C89183AF - 18 - rev. 0.7 jan. 2005 t dspsth lal (after rda) t is t ih t ch t cl t ck ck ck input (control & addresses) write timing (burst length = 4) desl 0123456789101112131415161718 q0 t dsp t dqss t dsp t dsp t dss t dh q1 q2 q3 t dspres t dspreh t dspst t dss t dspsth postamble preamble t dspre t ds t ds t dh t dqss t dh t ds cas latency = 4 lds/uds (input) dq (input) q0 t dsp t dsp t dsp t dh q1 q2 q3 t dspres t dspreh t dspst t dss postamble preamble t dspre t ds t ds t dh t dh t ds cas latency = 5 lds/uds (input) dq (input) t dss lqs/uqs (uni-qs) lqs/uqs (free runninig) low unidirectional ds/qs mode, unidirectional ds/free running qs mode note : dq0 to dq17 are sampled at both edges of lds. dq18 to dq35 are sampled at both edges of uds. t dspsth t dqss q0 t dsp t dsp t dsp t dh q1 q2 q3 t dspres t dspreh t dspst t dss postamble preamble t dspre t ds t ds t dh t dh t ds cas latency = 6 lds/uds (input) dq (input) t dss K4C89183AF - 19 - rev. 0.7 jan. 2005 command clk clk input (control & addresses) t is t ih t refi , t pause , ixxxx timing t is t ih command t refi, t pause, i xxxx note. " i xxxx "means " i rc ", " i rcd ", " i ras ", etc. ~ ~ ~ ~ K4C89183AF - 20 - rev. 0.7 jan. 2005 function truth table (notes : 1,2,3) command truth table (notes : 4) ?the first command symbol function cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 desl device deselect h x x x x x x rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ?the second command (the next clock of rda or wra command) notes : 1. l = logic low, h = logic high, x = either l or h, v = valid (specified value), ba = bank address, ua = upper address , la = lower address. 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latched on the crossing point of differential clock input where clk goes to high. 4. operation mode is decided by t he comination of 1st command and 2nd command refer to "state diagram" and the command table below. symbol function cs fn ba1-ba0 a14-a13 a12-a11 a10-a9 a8 a7 a6-a0 lal lower address latch h x x v x x x x la ref auto-refresh l x x x x x x x x mrs mode register set l x v l l l l v v read command table command (symbol) cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h x x x x x la write command table notes : 5. a14~a13 are used for variable write length (vw) control at write operation. command (symbol) cs fn ba1- ba0 a14 a13 a12 a11 a10~ a9 a8 a7 a6-a0 wra (1st) l l bauauauauauauauaua lal (2nd) hxxvw0vw1xxxxxla vw truth table function vw0 vw1 bl = 4 reserved l l write all words h l write first two words l h write first one word h h K4C89183AF - 21 - rev. 0.7 jan. 2005 auto-refresh command table function command (symbol) current state pd cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes n-1 n active wra(1st) standby h h l l x x x x x auto-refresh ref(2nd) active h h l x x x x x x power down table notes : 7. pd has to be brought to low within t fpdl from ref command. 8. pd should be brought to low after dq?s state turned high impedance. 9. when pd is brought to high from low, this function is executed asynchronously. function command (symbol) current state pd cs fn ba1- ba0 a14-a9 a8 a7 a6-a0 notes n-1 n power down entry pden standby h l h x x x x x x 8 power down continue - power down l l x x x x x x x power down exit pdex power down l h h x x x x x x 9 mode register set command truth table note : 6. refer to "mode register table". command (symbol) cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes rda (1st) l h x x x x x mrs (2nd) l x v l l v v 6 function truth table (continued) K4C89183AF - 22 - rev. 0.7 jan. 2005 function truth table (continued) notes : 10. illegal if any bank is not idle. 11. illegal to bank in specified states : function may be legal in the bank indicated by bank address (ba). 12. illegal if t fpdl is not stisfied. current state pd cs fn address command action notes n-1 n idle h h h x x desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h x x pden power down entry 10 h l l x x - illegal l x x x x - refer to power down state row active for read h h h x la lal begin read h h l x op-code mrs/emrs access to mode register h l h x x pden illegal h l l x x mrs/emrs illegal l x x x x - invalid row active for write h h h x la lal begin write h h l x x ref auto-refresh h l h x x pden illegal h l l x x ref (self) self-refresh entry l x x x x - invalid read h h h x x desl continue burst read to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h x x pden illegal h l l x x - illegal l x x x x - invalid write h h h x x desl data write & continue burst write to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h x x pden illegal h l l x x - illegal l x x x x - invalid auto-refreshing h h h x x desl nop-> idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h x x pden self-refresh entry 12 h l l x x - illegal l x x x x - refer to self-refreshing state mode register accessing h h h x x desl nop-> idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h x x pden illegal h l l x x - illegal l x x x x - invalid power down h x x x x - invalid l l x x x - maintain power down mode l h h x x rdex exit power down mode->idle after t pdex l h l x x - illegal K4C89183AF - 23 - rev. 0.7 jan. 2005 mode register table regular mode register (notes : 1) address ba1 *1 ba0 *1 a14-a8 a7 *3 a6-a4 a3 a2-a0 register 0 0 0 tm cl bt bl a7 test mode (te) 0 regular (default) 1 test mode entry a3 burst type (bt) 0 sequential 1 interleave a6 a5 a4 cas latency (cl) 00x reserved *2 010 reserved *2 011 reserved *2 100 4 101 5 110 6 111 reserved *2 a2 a1 a0 burst length (bl) 000 reserved *2 001 reserved *2 010 4 011 reserved *2 1xx extended mode register (notes : 4) address ba1 *4 ba0 *4 a14-a7 a6~a5 a4-a3 a2~a1 a0 *5 register 0 1 0 ss dic(qs) dic(dq) ds qs dq output driver impedance control (dic) a4 a3 a2 a1 0000 normal output driver 0101 str ong output driver 1010 weak output driver 1111 reserved a0 dll switch (ds) 0 dll enable 1 dll disable note : 1. regular mode register is chosen using the combinat ion of ba0 = 0 and ba1 = 0. 2. "reserved" places in regular mode register should not be set. 3. a7 in regular mode register must be set to "0"(low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combi nation of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation. a6 a5 strobe select 00 reserved *2 01 reserved *2 1 0 unidirectional ds/qs 1 1 unidirectional ds/free running qs K4C89183AF - 24 - rev. 0.7 jan. 2005 state diagram power down standby (idle) mode register auto- refresh active (restore) active write (buffer) read pdex (pd = h) pd = h lal lal ref mrs rda wra pden (pd = l) the second command at active state must be issued 1clock after rda or wra command input command input automatic return - 25 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 timing diagrams single bank read timing (cl=4) clk clk command address rda desl lal rda desl lal rda desl lal rda la ua la ua la ua ua #0 #0 #0 #0 unidirectional ds/qs mode bank add. (output) qs (output) dq (input) ds unidirectional ds/free running qs mode q0 q1 q2 q3 q0 q1 q2 q3 q0 q0 q1 q2 q3 q0 q1 q2 q3 q0 l rc =5cycles l rc =5cycles l rc =5cycles l rcd =1cycle l ras =4cycles l rcd =1cycle l ras =4cycles l rcd =1cycle l ras =4cycles low cl=4 hi-z cl=4 cl=4 cl=4 hi-z cl=4 cl=4 (output) qs (output) dq (input) ds - 26 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank read timing (cl=5) command address rda desl lal #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode q0 q1 q2 q3 q0 q1 q2 q3 l rc =6cycles low hi-z rda desl lal l rc =6cycles rda desl lal ua la l ras =5cycles l rcd =1cycle l ras =5cycles l rcd =1cycle ua la l rcd =1cycle ua la #0 #0 cl=5 cl=5 q0 q1 q2 q3 q0 q1 q2 q3 hi-z cl=5 cl=5 clk clk (output) qs (output) dq (input) ds (output) qs (output) dq (input) ds - 27 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank read timing (cl=6) command address rda desl lal #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode q0 q1 q2 q3 q0 q1 q2 l rc =7cycles low hi-z ua la l ras =6cycles l rcd =1cycle cl=6 cl=6 rda desl lal l rc =7cycles rda lal ua la l ras =6cycles l rcd =1cycle ua la #0 #0 q0 q1 q2 q3 q0 q1 q2 hi-z cl=6 cl=6 l rcd =1cycle clk clk (output) qs (output) dq (input) ds (output) qs (output) dq (input) ds - 28 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank write timing (cl=4) command address wra desl lal wra desl lal wra desl lal wra la ua la ua la ua ua #0 #0 #0 #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode (output) qs (input) dq (input) ds l rc =5cycles l rc =5cycles l rc =5cycles l rcd =1cycle l ras =4cycles l rcd =1cycle l ras =4cycles l rcd =1cycle l ras =4cycles (output) qs (input) dq (input) ds d0 d1 low wl=3 wl=3 d2 d3 d0 d1 d2 d3 wl=3 d0 d1 d2 d3 d0 d1 wl=3 wl=3 d2 d3 d0 d1 d2 d3 wl=3 d0 d1 d2 d3 clk clk - 29 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank write timing (cl=5) command address wra desl lal la ua #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode l rc =6cycles l rcd =1cycle l ras =5cycles (output) qs (input) dq (input) ds d0 d1 low d2 d3 wra desl lal l rc =6cycles wra desl lal la ua l rcd =1cycle l ras =5cycles la ua l rcd =1cycle #0 #0 d0 d1 d2 d3 wl=4 wl=4 d0 d1 d2 d3 d0 d1 d2 d3 wl=4 wl=4 clk clk (output) qs (input) dq (input) ds - 30 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank write timing (cl=6) command address wra desl lal la ua #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode (output) qs (input) dq (input) ds l rc =7cycles l rcd =1cycle l ras =6cycles (output) qs (input) dq (input) ds d0 d1 low d2 d3 wra desl lal la ua l rc =7cycles l rcd =1cycle l ras =6cycles wra lal la ua l rcd =1cycle #0 #0 d0 d1 d2 d3 wl=5 wl=5 d0 d1 d2 d3 d0 d1 d2 d3 wl=5 wl=5 clk clk - 31 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank read-write timing (cl=4) command address rda desl lal wra desl lal rda desl lal wra la ua la ua la ua ua #0 #0 #0 #0 unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode (output) qs dq (input) ds l rc =5cycles l rc =5cycles l rc =5cycles (output) qs dq (input) ds q0 q1 q2 q3 cl=4 cl=4 wl=3 low d0 d1 d2 d3 q0 q0 q1 q2 q3 cl=4 cl=4 wl=3 d0 d1 d2 d3 q0 hi-z hi-z clk clk - 32 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank read-write timing (cl=5) unidirectional ds/qs mode bank add. unidirectional ds/free running qs mode (output) qs dq (input) ds (output) qs dq (input) ds q0 q1 q2 q3 low d0 d1 d2 d3 hi-z command address rda desl lal la ua l rc =6cycles wra desl lal l rc =6cycles rda desl lal la ua la ua #0 #0 #0 cl=5 wl=4 q0 q1 q2 q3 d0 d1 d2 d3 hi-z cl=5 wl=4 read data write data clk clk - 33 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 single bank read-write timing (cl=6) unidirectional ds/qs mode unidirectional ds/free running qs mode q0 q1 q2 q3 low d0 d1 d2 d3 hi-z cl=6 wl=5 read data write data command address rda desl lal la ua #0 bank add. l rc =7cycles wra desl lal la ua l rc =7cycles rda lal la ua #0 #0 (output) qs dq (input) ds (output) qs dq (input) ds q0 q1 q2 q3 d0 d1 d2 d3 hi-z cl=6 wl=5 clk clk - 34 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank read timing (cl=4) unidirectional ds/qs mode unidirectional ds/free running qs mode command address rda lal la ua bank bank add. rda lal desl rda lal rda lal rda lal rda lal rda lal rda la ua la ua la ua la ua la ua la ua ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" bank "b" l rbd =2cycles qa0 qa1 cl=4 low hi-z (output) qs dq (input) ds qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 cl=4 (output) qa2 qa3 qb2 qb3 qa2 qa3 qb2 qb3 qc2 qa0 qa1 cl=4 hi-z (output) qs dq (input) ds qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 cl=4 (output) qa2 qa3 qb2 qb3 qa2 qa3 qb2 qb3 qc2 l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=5cycles l rc (bank"b")=5cycles clk clk note : l rc to the same bank must be satisfied - 35 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank read timing (cl=5) unidirectional ds/qs mode unidirectional ds/free running qs mode command address rda lal la ua bank bank add. rda lal desl rda lal rda lal rda lal rda lal rda lal la ua la ua la ua la ua la ua la ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" l rbd =2cycles qa0 qa1 low hi-z (output) qs dq (input) ds qb0 qb1 qa0 qa1 qb0 qb1 (output) qa2 qa3 qb2 qb3 qa2 qa3 qb2 (output) qs dq (input) ds (output) l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=6cycles l rc (bank"6")=6cycles cl=5 cl=5 qa0 qa1 hi-z qb0 qb1 qa0 qa1 qb0 qb1 qa2 qa3 qb2 qb3 qa2 qa3 qb2 cl=5 cl=5 clk clk note : l rc to the same bank must be satisfied - 36 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank read timing (cl=6) unidirectional ds/qs mode unidirectional ds/free running qs mode command address rda lal la ua bank bank add. rda lal desl rda lal rda lal rda lal rda lal rda la ua la ua la ua la ua la ua ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" l rbd =2cycles qa0 qa1 low hi-z (output) qs dq (input) ds qb0 qb1 qa0 qa1 (output) qa2 qa3 qb2 qb3 qa2 (output) qs dq (input) ds (output) l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=7cycles l rc (bank"b")=7cycles cl=6 cl=6 qa0 qa1 hi-z qb0 qb1 qa0 qa1 qa2 qa3 qb2 qb3 qa2 cl=6 cl=6 clk clk note : l rc to the same bank must be satisfied - 37 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank write timing (cl=4) unidirectional ds/qs mode unidirectional ds/free running qs mode command address wra lal la ua bank bank add. wra lal desl wra lal wra lal wra lal wra lal wra lal wra la ua la ua la ua la ua la ua la ua ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" bank "b" l rbd =2cycles da0 da1 low (output) qs dq (input) ds db0 db1 da0 da1 db0 db1 dc0 dc1 (input) da2 da3 db2 db3 da2 da3 db2 db3 dc2 (output) qs dq (input) ds (input) l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=5cycles l rc (bank"b")=5cycles dc3 dd0 dd1 wl=3 wl=3 da0 da1 db0 db1 da0 da1 db0 db1 dc0 dc1 da2 da3 db2 db3 da2 da3 db2 db3 dc2 dc3 dd0 dd1 wl=3 wl=3 clk clk note : l rc to the same bank must be satisfied - 38 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank write timing (cl=5) unidirectional ds/qs mode unidirectional ds/free running qs mode command address bank add. da0 da1 low (output) qs dq (input) ds db0 db1 da0 da1 db0 db1 dc0 dc1 (input) da2 da3 db2 db3 da2 da3 db2 db3 (output) qs dq (input) ds (input) wra lal la ua bank wra lal desl wra lal wra lal wra lal wra lal wra lal la ua la ua la ua la ua la ua la ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=6cycles l rc (bank"b")=6cycles wl=4 wl=4 da0 da1 db0 db1 da0 da1 db0 db1 dc0 dc1 da2 da3 db2 db3 da2 da3 db2 db3 wl=4 wl=4 note :i rc to the same bank must be satisfied. clk clk - 39 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank write timing (cl=6) unidirectional ds/qs mode unidirectional ds/free running qs mode command address bank add. da0 da1 low (output) qs dq (input) ds db0 db1 da0 da1 db0 db1 (input) da2 da3 db2 db3 da2 da3 (output) qs dq (input) ds (input) wl=5 wl=5 note :i rc to the same bank must be satisfied. wra lal la ua bank wra lal desl wra lal wra lal wra lal wra lal wra la ua la ua la ua la ua la ua ua "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rbd =2cycles l rc (bank"a")=7cycles l rc (bank"a")=7cycles da0 da1 db0 db1 da0 da1 db0 db1 da2 da3 db2 db3 da2 da3 wl=5 wl=5 clk clk - 40 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 wl=3 cl=4 low unidirectional ds/qs mode da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 qb2 qb3 low da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 qb2 qb3 low da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 wl=4 cl=5 wl=5 cl=6 cl =4 (output) qs dq (input) ds (output) cl =5 (output) qs dq (input) ds (output) cl =6 (output) qs dq (input) ds (output) multiple bank read-write timing (bl=4) command address wra lal la ua bank bank add. rda lal desl wra lal rda lal desl wra lal rda lal la ua la ua la ua ua ua la la "a" bank "b" bank "c" bank "d" l rbd =2cycles bank "a" bank "b" l rc (bank"a") l rc (bank"a") l wrd =1cycle l rwd =3cycles l wrd =1cycle l rwd =3cycles l wrd =1cycle note :i rc to the same bank must be satisfied. clk clk - 41 - K4C89183AF 0 234567891011 1 12 13 14 15 rev. 0.7 jan. 2005 multiple bank read-write timing (bl=4) command address wra lal la ua bank bank add. rda lal desl wra lal rda lal desl wra lal rda lal la ua la ua la ua ua ua la la "a" bank "b" bank "c" bank "d" l rbd =2cycles bank "a" bank "b" l rc (bank"a") l rc (bank"a") unidirectional ds/free running qs mode l wrd =1cycle l rwd =3cycles l wrd =1cycle l rwd =3cycles l wrd =1cycle wl=3 cl=4 da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 qb2 qb3 da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 qb2 qb3 da0 da1 qb0 qb1 hi-z da2 da3 qb2 qb3 da0 da1 qb0 qb1 da2 da3 wl=4 cl=5 wl=5 cl=6 note :i rc to the same bank must be satisfied. clk clk cl =4 (output) qs dq (input) ds (output) cl =5 (output) qs dq (input) ds (output) cl =6 (output) qs dq (input) ds (output) K4C89183AF - 42 - rev. 0.7 jan. 2005 write with variable write length (vw) control(cl=4) command wra lal desl wra lal bl=2, sequential mode desl address ua la=#3 ua vw=all la=#1 vw=1 bank add. bank bank "a" (input) dq (input) ds d0 d1 d0 lower address #3 #2 #1 (#0) last one data is masked. command wra lal desl wra lal bl=4, sequential mode desl address ua la=#3 ua vw=all la=#1 vw=1 bank add. bank "a" (input) dq (input) ds d0 d1 d0 lower address #3 #0 #1 #2 #1 (#2) (#3) (#0) last three data are masked. bank "a" desl wra lal ua la=#2 vw=2 bank "a" d2 d3 d0 d1 #2 #3 (#0) (#1) last two data are masked. note : ds input must be continued till end of burst count even if some of laster data is masked. 0 234567891011 1 12 13 14 15 clk clk vw0 = low vw1 = don?t care vw0 = high vw1 = don?t care "a" vw0 = high vw1 = low vw0 = high vw1 = high vw0 = low vw1 = high K4C89183AF - 43 - rev. 0.7 jan. 2005 power down timing (cl=4, bl=4) command rda lal rda bl=2, sequential mode address ua ua desl or wra la unidirectional ds/free running qs mode unidirectional ds/qs mode pd t ih t qpdh t pdex t is i pd =2 cycle i rc(min), t refi(max) q0 q1 low hi-z (output) qs dq (input) ds (output) cl=4 q2 q3 q0 q1 hi-z (output) qs dc (input) ds (output) cl=4 q2 q3 hi-z hi-z pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied i pda cycles later. note : power down entry p ower down exit 0 2345678910n-1 1 nn+1n+2n+3 clk clk read cycle to power down mode desl i pda K4C89183AF - 44 - rev. 0.7 jan. 2005 power down timing (cl=4, bl=4) command wra lal address ua desl la unidirectional ds/free running qs mode unidirectional ds/qs mode pd t ih t pdex t is i pd =2 cycle i rc(min), t refi(max) low (output) qs dc (input) ds (output) wl=3 (output) qs dc (input) ds (output) d0 d1 d2 d3 wl=3 i pd =2 cycle d0 d1 d2 d3 wl=3 pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied i pda cycles later. note : 0 2345678910n-1 1 nn+1n+2n+3 i pda write cycle to power down mode clk clk rda ua or wra desl K4C89183AF - 45 - rev. 0.7 jan. 2005 0 234567891011 1 12 13 14 15 mode register set timing (cl=4, bl=4) command a14~a0 wra desl lal la ua ba ba0, ba1 rda desl mrs l rc =7cycles lal la ua ba1="0" ba rda or wra ba0="0" (opcode) valid from write operation to m ode register set operation unidirectional ds/free running qs mode (output) qs dc (input) ds (input) (output) qs dc (input) ds low (output) qs dc (input) ds (output) qs dc (input) ds d0 d1 d2 d3 d0 d1 d2 d3 unidirectional ds/qs mode (input) note : minimum delay from lal following wra to rda of mrs operation is wl+bl/2. clk clk wl + bl/2 K4C89183AF - 46 - rev. 0.7 jan. 2005 extended mode register set timing (cl=4, bl=4) command a14~a0 wra desl lal la ua ba ba0, ba1 rda desl mrs l rc =7cycles lal la ua ba1="0" ba rda or wra ba0="0" (opcode) valid from write operation to extended mode register set operation when dq strobe mode is changed by emrs, qs output is invalid for i rsc period. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. minimum delay from lal following wra to rda of emrs operation is wl+bl/2. note : unidirectional ds/free running qs mode (output) qs dc (input) ds (input) (output) qs dq (input) ds low (output) qs dq (input) ds (output) qs (input) ds d0 d1 d2 d3 d0 d1 d2 d3 unidirectional ds/qs mode (input) 0 234567891011 1 12 13 14 15 clk clk wl + bl/2 K4C89183AF - 47 - rev. 0.7 jan. 2005 0 234567n-1nn+1n+2 1 auto-refresh timing (cl=4, bl=4) rda lal desl wra ref desl rda bank, la command bank, address or wra lal or mrs or ref ua q0 q1 q2 q3 qs (output) dq (output) unidirectional ds/free running qs mode cl=4 l rc =5cycles l refc =19cycles l rcd =1cycle l ras =4cycles l rcd =1cycle low hi-z low hi-z rda lal desl wra ref desl rda bank, la command bank, address or wra lal or mrs or ref ua q0 q1 q2 q3 qs (output) dq (output) cl=4 l rc =5cycles l refc =19cycles l rcd =1cycles l ras =4cycles l rcd =1cycles hi-z hi-z in case of cl=4, i refc must be meet 19 clock cycles. when the auto-refresh operation is perfomed, the synthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refresh cycles that is sampled randomly. note : unidirectional ds/qs mode wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle total time of 8 refresh cycle 8 t 1 +t 2 +t 3 +t 4 +t 5 +t 6 +t 7 +t 8 8 = t refi = t refi is specified to avoid partly concentrated current of refresh operation that is acivated larger are than read/write operation. clk clk clk clk clk K4C89183AF - 48 - rev. 0.7 jan. 2005 function description network - dram network - dram is an acronym of d ouble data rate network - dram. network - dram is competent to perform fast random core access, low latency and high-speed data transfer. pin functions clock inputs : clk & clk the clk and clk inputs are used as the reference for synchronous operation. clk is master clock input. the cs , fn and all address input signals are sampled on the crossing of the positive edge of clk and the negative edge of clk . the qs and dq output data are aligned to the crossing point of clk and clk . the timing reference point for the diff erential clock is when the clk and clk signals cross during a transition. power down : pd the pd input controls the entry to the powe r down or self-refresh modes. the pd input does not have a cl ock suspend function like a cke input of a standard sdrams, therefore it is illegal to bring pd pin into low state if any read or write operation is being per- formed. chip select & function control : cs & fn the cs and fn inputs are a control signal for forming the operati on commands on network-dram. each operation mode is decided by the combination of the two consec utive operation commands using the cs and fn inputs. bank addresses : ba0 & ba1 the ba0 and ba1 inputs are latched at the time of assertion of the rda or wra command and are selected the bank to be used for the operation. ba0 and ba1 also define which mode register is loaded during the mode register set command (mrs or emrs). address inputs : a0 to a14 address inputs are used to access the arbi trary address of the memory cell array with in each bank. the upper addresses with b ank address are latched at the rda or wra command and the lower a ddresses are latched at the lal command. the a0 to a14 inputs are also used for setting the data in the regular or extended mode register set cycle. ba0 ba1 bank #0 0 0 bank #1 1 0 bank #2 0 1 bank #3 1 1 upper address lower address K4C89183AF a0 to a14 a0 to a6 K4C89183AF - 49 - rev. 0.7 jan. 2005 functional description (continued) data input/output : dq0 ~ dq17 the input data of dq0 to dq17 are taken in sync hronizing with the both edges of ds input signal. the output data of dq0 to dq17 ar e outputted synchronizing with the bo th edges of qs output signal. data strobe : ds or qs method of data strobe is chos en by extended mode register. (1) unidirectional ds/qs mode ds is input signal and qs is output signal. both edges of ds ar e used to sample all dqs at write operation. both edges of qs are used for trigger signal of all dqs at read operation. duri ng write. auto-refresh and nop cy cle, qs assert always "low" level. qs is hi-z in self-refresh mode. (2) unidirectional ds/free running qs mode ds is input signal and qs is output signal. both edges of ds ar e used to sample all dqs at write operation. both edges of qs are used for trigger signal of all dqs at read operation. qs asse rt always toggle signal except self-refresh mode. this strobe type is easy to use for pin to pin connect application. power supply : v dd , v ddq , v ss , v ssq v dd and v ss are supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage : v ref v ref is reference voltage for all input signals. K4C89183AF - 50 - rev. 0.7 jan. 2005 command functions and operations k4c89093af is introduced the two consecut ive command input method. t herefore, except for powe r down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with b ank addresses and upper addresses to the idle ban k puts the bank designate d by bank address in a read mode. when the lal command with lower addresses is issued at the next cloc k of the rda command, the data is read out sequentially synchronizing with the both ed ges of qs output signal (burst read oper ation). the initial valid read data appears after cas latency, the burst length of read data a nd the burst type must be set in the mode register beforehand. the read operated bank goes back automatically to the idle state after i rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal comm and with lower addresses is iss ued at the next clock of the wra command, the input data is latched sequentially synchronizing with the both edges of ds input signal (burst write operation). the data and ds inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal co mmand. the ds have to be provided for a burst length. the cas latency and the burst type must be set in the mode regi ster beforehand. the write oper ated bank goes back automat- ically to the idle state after i rc . write burst length is controll ed by vw0 and vw1 inputs with la l command. see vw truth table. auto-refresh operation (1st command + 2nd command = wra + ref) k4c89093af is required to refresh like a standard sdram. the auto-refresh operation is begun wi th the ref command following t o the wra command. the auto-r efresh mode can be effective only when all banks are in the idle state and all dq are in hi-z states . in a point to notice, the write mode started wi th the wra command is cancel ed by the ref command having gone into the next clock o f the wra command instead of the lal comm and. the minimum period between the auto -refresh command and t he next command is specified by i refc . however, about a synthetic average interv al of auto-refresh command, it must be careful. in case of equally distrib- uted refresh, auto-refresh command has to be issued within once for every 3. 9 us by the maximum in case of burst refresh or ran dom distributed refresh, the average in terval of eight consec utive auto-refresh command has to be more than 400ns always. in other words, the number of auto-refresh cy cles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum. power down mode( pd ="l" ) when all banks are in the idle state and all dq outputs are in hi-z states, the K4C89183AF become power down mode by assertin g pd is "low". when the device enters the power down mode, all input and output buffers except for pd , clk, clk and qs. therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to "high" an d the desl command has to be issued for i pda cycle after pd goes high. the power down exit function is asynchronous operation. mode register set (1st command + 2nd command = rda + mrs) when all banks are in the idle state, issuing the mrs command following to the rd a command can program t he mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs command hav ing gone into the next clock of the rda command instead of the lal command. the data to be set in t he mode register is transferred using a0 to a14, ba0 and ba1 address inputs. the K4C89183AF hav e two mode registers. these are regular and e xtended mode register. the regular or extended mode register is chosen by ba0 and ba1 in the mrs command.the r egular mode register designates the operation mode for a read or write cycle. the regular mode re gister has four function fields. K4C89183AF - 51 - rev. 0.7 jan. 2005 the four fields are as follows : (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lowe r address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has two function fields. the two fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver impedance control field. (e-3) data strobe select once these fields in the mode register are set up, the register contents are maintained until the mode register is set up agai n by another mrs command or power supply is lost. the initial value of the regular or extended mode register after power-up is unde- fined, therefore the mode register set comman d must be issued before proper operation. ? regular mode register/extended mode register change bits (ba0, ba1) these bits are used to choo se either regular mrs or extended mrs regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 4 words. (r-2) burst type field (a3) this burst type can be chosen interleave mode or sequential mode. when the a3 bit is " 0", sequential mode is selected. when the a3 bit is "1", interl eave mode is selected. both burst types support burst length of 2 and 4 words. ? addressing sequence of sequential mode (a3) a column access is started from the inputted lower address an d is performed by incrementing the lower address input to the device. ba1 ba0 a14~a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1xreserved a2 a1 a0 burst length 000reserved 001reserved 010 4 words 011reserved 1 x x reserved a3 burst type 0 sequential 1 interleave K4C89183AF - 52 - rev. 0.7 jan. 2005 rda lal data 0 data 1 data 2 data 3 addressing sequence for sequential mode data access address burst length data 0 n 4 words(address bits is la1, la0) not carried from la1~la2 data 1 n + 1 data 2 n + 2 data 3 n + 3 cas latency = 4 (free running qs mode) ck ck command qs dq functional description (continued) ? addressing sequence of inteleave mode a column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode (r-3) cas latency field (a6 to a4) this field specifies the numbe r of clock cycles from the assertion of t he lal command followin g the rda command to the first data read. the minimum values of cas latency depends on the frequency of clk. in a write mode, the place of clock which should input write data is cas latency cycles - 1. data access address burst length data 0 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 4 words data 1 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 data 3 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 addressing sequence for interleave mode a6 a5 a4 cas latency 000 reserved 001 reserved 010 reserved 011 reserved 100 4 101 5 110 6 111 7 K4C89183AF - 53 - rev. 0.7 jan. 2005 (r-4) test mode field (a7) this bit is used to enter test mode for supplier only and must be set to "0" for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a14) these bits are reserved for future operations. they must be set to "0 " for normal operation. extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is set "0", dll is enabled. (e-2) output driver impedance control field (a1 to a4) this field is used to choose output dr iver strength. four types of driver stre ngth are supported. qs and dq driver strength can be chosen separately. a2-a1 specified the dq driver strength. a4-a3 specified the qs driver strength. (e-3) strobe select (a6/a5) two types of strobe are supported. this field is used to choose the type of data strobe. (1) unidirectional ds/qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write oper ation. qs is aligned with read data at read operation. (2) unidirectional ds/f ree running qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write operation. qs is aligned with read data and always clocking (e-4)reserved fied (a7 to a14) these bits are reserved for future operations and must be set to "0" for normal operation. qs dq output driver impedance control a4 a3 a2 a1 0000 normal output driver 0101 strong output driver 1010 weaker output driver 1111 reserved a6 a5 strobe select 00 reserved 01 reserved 1 0 unidirectional ds/qs mode 1 1 unidirectional ds/free running qs mode K4C89183AF - 54 - rev. 0.7 jan. 2005 package outline drawing (fbg a 60ball, 1.0 x 1.0 mm) 10.50 0.10 15.50 0.10 15.50 0.10 0.10 max 0.5 0.05 0.35 0.05 1.10 0.10 window mold area top view 1 3 4 5 6 10.50 0.10 a b c d e f g h j k l m 7.00 1.00 x 14 = 14.00 15.50 0.10 7.00 1.00 x 5 = 5.00 bottom view 1.00 1.00 p r 1.50 1.50 2 1.00 60 - ? 0.45 solder ball 2.50 #a1 mark (option) #a1 n K4C89183AF - 55 - rev. 0.7 jan. 2005 general information f6 : 667mbps/pin (333mhz, cl=6) fb : 600mbps /pin (300mhz, cl=6) f5 : 500mbps/pin (250mhz, cl=6) c : (commercial, normal) i : (industrial, normal) 08 : x8 09 : x9 16 : x16 18 : x18 89 : 288m 8k/32ms c : network-dram f : 7th generation k 4 c xx xx x x x - x x memory dram small classification density and refresh temperature & power package organization version interface (vdd & vddq) 1. samsung memory : k 2. dram : 4 3. small classification 4. density & refresh 5. organization 8. version 9. package 10. temperature & power 11. speed 3 : 4 bank 6. bank 1 2 3 4 5 6 7 8 9 10 11 xx a : sstl-2(2.5v, 1.8v) 7. interface (vdd & vddq) speed bank organization f6 (667mbps@cl6) fb (600mbps@cl6 ) f5 (500mbps@cl6 ) 288m(x9) k4c89093af-acf6 k4c890 93af-acfb k4c89093af-ac(i)f5 288m(x18) K4C89183AF-acf6 k4c891 83af-acfb K4C89183AF-ac(i)f5 288m(x36) k4c89363af-gcf6 k4c8 9363af-gcfb k4c89363af-gc(i)f5 a : 60 fbga g : 144 fbga |
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